1. Field of the Invention
The present invention relates to an information processing apparatus comprising a reconfigurable device capable of changing the circuits constructed within the reconfigurable device and a method for using the reconfigurable device.
2. Description of the Related Art
In the field of information processing, the application range of information processing apparatus has been extended and the requirement is that these apparatuses have the capability of performing faster arithmetic operations or of handling large amounts of data, such as still images or moving pictures, at high speeds. The means for meeting such requirements are conventionally well known and these comprise a DSP (Digital Signal Processor) or an ASIC (Application Specific Integrated Circuit) for managing a specific arithmetic operation or process separately from the CPU, and improves the processing ability of the information processing apparatus by reducing the processing load of the CPU.
However, in recent years the requirement has been that information processing apparatus have a compression/decompression algorithm or an arithmetic operation algorithm in conformity with various standards for multi-media data such as still images, moving pictures, voice and music, and the information processing apparatuses employ various communication protocols for transmitting or receiving various kinds of data via a network such as the Internet. Further, to deal with the problem of safeguarding information that is transmitted or received on the network, an encryption and a decryption process are needed. Therefore, if a number of DSPs or ASICs are provided in accordance with these processes, the circuit scale or cost of the information processing apparatus will be greatly increased.
Thus, it is well known that information processing apparatuses have a reconfigurable device such as FPGA (Field Programmable Gate Array) or DRP (Dynamically Reconfigurable Processor), and perform the process by rewriting a program within the reconfigurable device, as needed, whereby throughput processing capability of the information processing apparatus is improved to better handle various processing requests with the reduced costs.
The reconfigurable device comprises an internal memory for storing the program (configuration code) inside, in which the configuration code stored in an external memory is loaded into the internal memory under the control of the CPU. And a virtual circuit is constructed internally in accordance with the loaded configuration code, and a predetermined process (hereinafter referred to as a task) is performed for the data inputted by the virtual circuit.
Since the capacity of this internal memory is limited, the circuit scale implemented by the configuration code is also limited. In a case where two or more circuits that have a capacity equal to or more than that of the internal memory are built within the reconfigurable device, the reconfigurable device can not implement these circuits at the same time so that the reconfigurable device is required to perform the task while changing the configuration codes.
Usually, since the size of the configuration code is large, it takes a long time to load it into internal memory. Therefore, in the FPGA, it is proposed that even if a part of the circuit is operating, other circuit formation areas not operating can be changed For this configuration, for example, refer to Virtex2 (P. Butel, G. Habay, A Rachet, “Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs”, Xilinx, Inc., [Aug. 15, 2005], or Virtex4 (R. Krueger, “Dynamic Reconfiguration of Functional Blocks” Xilinx, Inc., [Aug. 15, 2005].
Also, in the DRP, even if a part of the circuit is operating, the configuration code for the context not in use can be rewritten from the outside. For example, its method is described in Japanese Patent Application Laid-Open No. 2004-133780 and Japanese Patent Application Laid-Open No. 2004-133781.
Also, as described in Japanese Patent Application Laid-Open No. 2005-124130, to automatically adjust processing time of the reconfigurable device in accordance with the processing capability required for each process, the amount of accumulated input and output data for the reconfigurable device is monitored, and the configuration code is read in accordance with the processing capability of the circuit.
Since the CPU usually inputs and processes instructions and data at the same time, the CPU may be considered to be the reconfigurable device. Japanese Patent Application Laid-Open No. 2000-040745 or Japanese Patent Application Laid-Open No. 2000-516418, for example, propose dynamically rewriting the process (circuit configuration) performed by the CPU, Also, it was offered in International Patent Publication No. 2001/090887 pamphlet to dynamically rewrite the program in accordance with the used cost value.
By the way, in the information processing apparatus, it may not be possible to solve the problem with the system only by implementing the circuit having its physical circuit area or more using the reconfigurable device. For example, it is not necessarily essential for the circuit that the circuit area be small, but high throughput processing capability or low power consumption may be required for data processing.
Also, these requirements that may be required are not absolute, but may be changed in accordance with the operation state of the system, as needed. For example, when the remaining a battery capacity that supplies power to the system is small, or when the ambient temperature of the apparatus rises, it will be necessary to limit power consumption of the circuit.